C.-Y Hu;M. Y. Song;G. L. Chen;K. M. Chen;K. T. Chang;I. J. Wang;Y. C. Hsin;S. Y. Yang;S. H. Li;J. H. Wei;T. Y. Lee;X. Y. Bao
{"title":"2T1M and Complementary 3T2M Type-XY SOT-MRAM With High Performance and High Density","authors":"C.-Y Hu;M. Y. Song;G. L. Chen;K. M. Chen;K. T. Chang;I. J. Wang;Y. C. Hsin;S. Y. Yang;S. H. Li;J. H. Wei;T. Y. Lee;X. Y. Bao","doi":"10.1109/LED.2025.3582797","DOIUrl":null,"url":null,"abstract":"Type-XY SOT-MRAM is promising to achieve smaller footprint compared to the type-Y cells, and to circumvent the non-deterministic characteristic suffered by the type-X switching. This work verifies the high performance of type-XY switching in a 2-transistor-1-memory (2T1M) array, showing the capability of low write-error-rate (<0.1%)> <tex-math>${8}\\times {10} ^{{11}}$ </tex-math></inline-formula>cycles@±0.8V/100ns) with low write error rate (<0.1%@1V/500ns).> <tex-math>$0.61\\times $ </tex-math></inline-formula> cell size with <inline-formula> <tex-math>$0.41\\times $ </tex-math></inline-formula> write power in traditional 2T1M, <inline-formula> <tex-math>$0.67\\times $ </tex-math></inline-formula> cell size with <inline-formula> <tex-math>$0.10\\times $ </tex-math></inline-formula> operation power in 3T2M for complementary write function. Considering the sharable processes between 2T1M and 3T2M, using type-XY cells can be a fabrication-friendly solution to facilitate the integration of multifunctional memories in the advanced chips.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 8","pages":"1341-1344"},"PeriodicalIF":4.5000,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11048946/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Type-XY SOT-MRAM is promising to achieve smaller footprint compared to the type-Y cells, and to circumvent the non-deterministic characteristic suffered by the type-X switching. This work verifies the high performance of type-XY switching in a 2-transistor-1-memory (2T1M) array, showing the capability of low write-error-rate (<0.1%)> ${8}\times {10} ^{{11}}$ cycles@±0.8V/100ns) with low write error rate (<0.1%@1V/500ns).> $0.61\times $ cell size with $0.41\times $ write power in traditional 2T1M, $0.67\times $ cell size with $0.10\times $ operation power in 3T2M for complementary write function. Considering the sharable processes between 2T1M and 3T2M, using type-XY cells can be a fabrication-friendly solution to facilitate the integration of multifunctional memories in the advanced chips.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.