Kai Jiang;Ziheng Wang;Zhiyu Lin;Zhenyu Chen;Jinxiu Zhao;Liankai Zheng;Chen Wang;Siying Li;Shan-Ting Zhang;Dongdong Li;Xiuyan Li;Xiaojun Guo;Mengwei Si
{"title":"Top-Gate Atomic-Layer-Deposited Oxide Semiconductor Transistors With Large Memory Window and Non-Ferroelectric HfO₂ Gate Stack","authors":"Kai Jiang;Ziheng Wang;Zhiyu Lin;Zhenyu Chen;Jinxiu Zhao;Liankai Zheng;Chen Wang;Siying Li;Shan-Ting Zhang;Dongdong Li;Xiuyan Li;Xiaojun Guo;Mengwei Si","doi":"10.1109/LED.2025.3581599","DOIUrl":null,"url":null,"abstract":"In this work, we demonstrate a top-gate indium-zinc oxide (IZO) transistor with non-ferroelectric HfO2 gate stack but exhibiting a counterclockwise hysteresis loop with large memory window (MW) of 2.7 V and long retention over 10 years. The gate stack capacitor shows non-ferroelectricity in both P-V and C-V measurements. It is understood that oxygen vacancy formation at the O-poor interface is likely to be the origin of the counterclockwise hysteresis loop because the large MW disappears completely after high-temperature O2 annealing. This work suggests that the origin of the memory characteristics in oxide semiconductor ferroelectric field-effect transistors (FeFETs) need to be carefully justified due to the competing mechanism.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 8","pages":"1353-1356"},"PeriodicalIF":4.5000,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11045794/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, we demonstrate a top-gate indium-zinc oxide (IZO) transistor with non-ferroelectric HfO2 gate stack but exhibiting a counterclockwise hysteresis loop with large memory window (MW) of 2.7 V and long retention over 10 years. The gate stack capacitor shows non-ferroelectricity in both P-V and C-V measurements. It is understood that oxygen vacancy formation at the O-poor interface is likely to be the origin of the counterclockwise hysteresis loop because the large MW disappears completely after high-temperature O2 annealing. This work suggests that the origin of the memory characteristics in oxide semiconductor ferroelectric field-effect transistors (FeFETs) need to be carefully justified due to the competing mechanism.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.