A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique

Abstract

This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the $K_{\textrm {VCO}}$ , thereby eliminating the need for post-linearity calibration. Fabricated in a 28-nm FDSOI process, the ADC occupies an area of 0.009 mm2 and achieves an SNDR of 39.26 dB and an SFDR of 48.01 dB at 2.5 GS/s, while consuming 6.5 mW of power. This results in a Walden FOM of 34.6 fJ/conversion step.