Bus-Aware Ordered Escape Routing Under Bus-Direction Constraints

Abstract

It is known that ordered escape routing becomes more important in printed circuit board (PCB) designs. In this article, given a set of escape pins with some buses under bus-direction constraints inside a pin array, a set of available boundaries, and the capacity constraint between two adjacent pins, bus-aware ordered escape routing (BOER) under bus-direction constraints can be formulated and an efficient algorithm can be proposed to solve the routing problem. In ordered escape routing for the given buses, based on the locations of the escape pins for any bus with its bus-direction constraint, the target pins of the unrouted nets inside the bus can be first assigned onto the constrained boundary for length minimization and the unrouted nets inside the bus can be further routed for skew minimization. In ordered escape routing for the remaining nets, based on the routing results of the given buses as obstacles and the division of the remaining routing space, the remaining unrouted nets can be first partitioned into some net sets and the nets inside any net set can be further routed inside its specific routing region. Compared with Luo’s SAT-based algorithm, Jiao’s flow-based algorithm, and Yan’s algorithm with no bus-direction consideration, the proposed algorithm can obtain the 100% routability of the escape nets and reduces 38.6%, 34.4%, and 28.9% of the number of the violated buses on the average for the six tested examples with capacity as 1, respectively. Additionally, compared with Yan’s algorithm with no bus-direction consideration, the proposed algorithm can also achieve 100% routability of the escape nets and reduces 37.3% of the number of the violated buses on the average for the other six tested examples with capacity as 2.