Multiple-step Siconi pre-clean advantages for Ni(Pt)Si film formation in the frame of advanced FDSOI technology development

Abstract

In the development of 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology utilizing high-k metal gate transistors, Ni-based silicide contacts are essential for active silicon regions. The integration of metal gate transistors with the Ni(Pt)Si formation process presents significant challenges, particularly regarding surface preparation prior to Ni (10 at.% Pt) deposition. This step is critical as it can facilitate the propagation of Sulfuric Peroxide Mixture (SPM) chemistry during Ni(Pt)Si formation, potentially leading to the removal of the TiN layer within transistor gates, commonly referred to as "black gates”. To address these challenges, various NF₃/NH₃ dry pre-clean processes, known as the Siconi process, have been explored to enhance Ni(Pt)Si thin film formation at reduced dimensions without compromising the integrity of high-k metal gate structures. Notably, a multi-step Siconi process has significantly reduced non-uniformity issues of the Ni(Pt)Si thickness on blanket wafers. Additionally, a distinct distribution of fluorine species is observed at the interface between the intermixing layer and the silicon substrate, with potential new bond formations identified in multi-step processes. Furthermore, substantial improvements in silicide resistance and SRAM yield have been recorded, attributed to the reduction of "missing NiSi" and "black gates" defects through the implementation of this novel surface preparation approach.