A novel test items evaluation method for mixed-signal system-on-chips based on extra information gain cost

Abstract

As system-on-chip (SoC) grow increasingly complex, the number of test items required for accurate characterization continues to rise. However, the high test time necessitates efficient test process optimization. Although several studies have explored in digital chips, where test data are more accessible and scan chains enable efficient defect localization, these methods are often ineffective for analog chips. In mixed-signal SoC tests, advanced optimization algorithms typically rely on the posterior probability knowledge, which is usually unavailable under the stop-on-first-failure mechanism. To overcome these limitations, this paper proposes a novel test items evaluation method by introducing an extra information gain cost (EIGC) index. The proposed method is based on correlation analysis, where each test item is assessed throughout the entire test process without relying on failed chips’ database. It is validated through experiments on the final test and binning process of two mixed-signal SoC designs. Results demonstrate that reordering test sequences and pruning redundant test items based on the EIGC index can achieve a significant reduction in test time without defective chips escaping. To the best of our knowledge, for the first time, such an index is introduced to evaluate the SoC test items under stop-on-first-failure mechanism without requiring posterior probability knowledge.