Pressure-assisted large-area (50∗45 mm2) sintered-copper bonding for power modules

IF 4.6 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Materials Science in Semiconductor Processing Pub Date : 2025-06-14 DOI:10.1016/j.mssp.2025.109784

Dongfang Dai , Yexiong Huang , Kai Zheng , Jiabing Yu , Xianping Chen

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Abstract

- In this study, we demonstrate a novel copper paste encapsulated with copper formate, enabling robust large-area bonding (50 × 45 mm²) under remarkably mild conditions: middle pressure (10 MPa), rapid sintering (10 min), and low temperature (220 °C). A systematic investigation of the relationship between bonding strength and microstructural evolution is conducted. The bonded interface exhibits a low porosity of ∼10 % and achieves a bonding strength exceeding 60 MPa. Crucially, under pressures above 10 MPa, significant plastic deformation of the sintered copper is observed, accompanied by a marked reduction in surface roughness and a concomitant enhancement in bonding strength. Thermal simulations further indicate that the large-area sintered copper layer reduces the chip junction temperature by 6.6°C, highlighting its potential for thermal management applications. This breakthrough addresses the longstanding challenges of high energy consumption and inadequate bonding strength in large-scale sintering processes, offering a promising pathway for high-temperature applications in next-generation high-power devices.¹

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用于功率模块的压力辅助大面积（50 * 45 mm2）烧结铜键合

在这项研究中，我们展示了一种用甲酸铜封装的新型铜膏，在非常温和的条件下：中压（10 MPa）、快速烧结（10分钟）和低温（220°C）下，实现了坚固的大面积粘合（50 × 45 mm2）。系统地研究了结合强度与微观组织演变之间的关系。结合界面的孔隙率低，约为10%，结合强度超过60 MPa。最重要的是，在高于10兆帕的压力下，观察到烧结铜的显著塑性变形，伴随着表面粗糙度的显著降低和结合强度的增强。热模拟进一步表明，大面积烧结铜层使芯片结温降低了6.6°C，突出了其热管理应用的潜力。这一突破解决了大规模烧结过程中高能耗和结合强度不足的长期挑战，为下一代大功率器件的高温应用提供了一条有希望的途径

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来源期刊

Materials Science in Semiconductor Processing 工程技术-材料科学：综合

CiteScore

8.00

自引率

4.90%

发文量

780

审稿时长

42 days

期刊介绍： Materials Science in Semiconductor Processing provides a unique forum for the discussion of novel processing, applications and theoretical studies of functional materials and devices for (opto)electronics, sensors, detectors, biotechnology and green energy. Each issue will aim to provide a snapshot of current insights, new achievements, breakthroughs and future trends in such diverse fields as microelectronics, energy conversion and storage, communications, biotechnology, (photo)catalysis, nano- and thin-film technology, hybrid and composite materials, chemical processing, vapor-phase deposition, device fabrication, and modelling, which are the backbone of advanced semiconductor processing and applications. Coverage will include: advanced lithography for submicron devices; etching and related topics; ion implantation; damage evolution and related issues; plasma and thermal CVD; rapid thermal processing; advanced metallization and interconnect schemes; thin dielectric layers, oxidation; sol-gel processing; chemical bath and (electro)chemical deposition; compound semiconductor processing; new non-oxide materials and their applications; (macro)molecular and hybrid materials; molecular dynamics, ab-initio methods, Monte Carlo, etc.; new materials and processes for discrete and integrated circuits; magnetic materials and spintronics; heterostructures and quantum devices; engineering of the electrical and optical properties of semiconductors; crystal growth mechanisms; reliability, defect density, intrinsic impurities and defects.