A 15T SRAM Cell-Based Fully-Digital Computing-in-Memory Macro Supporting High Parallelism and Fine-Grained Simultaneous Read + Write + MAC Operations

Abstract

A 15-transistor (15T) SRAM cell-based fully-digital computing-in-memory (CIM) macro is proposed for artificial intelligence accelerations. The CIM macro not only supports simultaneous read + write + multiply-accumulate (MAC) operations, but also supports ultrawide-range voltage scaling, digital design flow, and cell-wise bit interleaving. A fine-grained weight update scheme is introduced to perform write and MAC operations simultaneously. A specialized two’s complement processing strategy is proposed to enable efficient signed MAC operations without in-array sign extension. Fabricated in a 55-nm CMOS technology, the proposed fully-digital CIM macro enhances the peak energy efficiency by up to $3.46\times $ compared with the state-of-the-art digital CIM schemes.