Impact of Pulse Voltage Stress on the Reliability of Ferroelectric Thin-Film Transistor

Abstract

Ferroelectric transistors can function as non-volatile memory devices with single-bit, multi-bit, and analog capabilities. State modulation is achieved by programming and erasing with bipolar pulse voltages, while a series of unipolar pulses enable synaptic potentiation and depression. This study examines the effect of pulse voltage stress on the reliability of ferroelectric thin-film transistors (FeTFT) with polycrystalline-silicon (poly-Si) ultra-thin body (UTB) channels. By applying various pulse stresses—bipolar, positive, and negative unipolar—with different pulse widths, we observed distinct degradation behaviors in UTB-FeTFT characteristics. Long bipolar pulse stress caused significant degradation due to the combined effects of the internal electric field from the ferroelectric layer and the external field. In contrast, short bipolar stress led to milder degradation, as lower remnant polarization reduced the total stress field. Rapid changes in electric field direction also limited charge accumulation in the channel, decreasing interface trap generation. Although short bipolar stress had minimal impact on subthreshold swing, it notably degraded maximum transconductance, primarily due to strain in the poly-Si channel’s atomic bonds. Enhancing device reliability is essential for improving FeTFT endurance.