Design Optimization of Flip FET Standard Cells With Dual-Sided Pins for Ultimate Scaling

Abstract

Recently, we proposed a novel transistor architecture for 3-D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dualsided interconnects. With dual-sided power rails and signal tracks, FFET can achieve an aggressive 2.5 T cell height. As a tradeoff, the complex structure and limited numbers of M0 tracks could limit the standard cell design. As a solution, multiple innovations were introduced and examined in this work. Based on an advanced node design rule, several unique building blocks in FFET such as drain merge (DM), gate merge (GM), field DM (FDM), and buried signal track (BST) were investigated. Other key design concepts of multi-row, split gate (SG), and dummy gate (DG) insertion were also carefully studied, delivering around 35.6% area reduction compared with 3 T CFET. Furthermore, the symmetric design of FFET has unique superiority over CFET thanks to the separate N/P logic on two sides of the wafer and their connections using DM and GM. New routing scheme with dual-sided output pins on both wafer frontside (FS) and backside (BS) was proposed for the first time. Finally, we conducted a comprehensive evaluation on complex cell design, taking AOI22 as an example. New strategies were proposed and examined. The FDM design is identified as the best, outperforming the BST and DG design by 1.93% and 5.13% for the transition delay.