Impact of incomplete ionization in presence of interface traps in p-i-n TFET and n-p-n double gate TFET

Abstract

This study investigates the impact of incomplete ionization and interface traps on the performance of p-i-n SOI Tunnel Field-Effect Transistors (TFETs) and n-p-n SOI double-gate TFETs, known for their low subthreshold swing and potential for low-power applications, are sensitive to both incomplete ionization of dopants and defects at the semiconductor-oxide interface. This research examines the interaction of these two phenomena and their influence on device sensitivity, focusing on single level and Gaussian trap distributions. Through comprehensive simulations using the Sentaurus TCAD tool, the study evaluates the effects of different trap distributions and doping levels on TFET performance. Results reveal that Gaussian traps exhibit higher sensitivity compared to single level traps, and incomplete ionization is more significant under negative gate-source voltages, leading to a reduction in available carriers. Additionally, temperature variations alter the sensitivity peaks of the devices, indicating that thermal effects influence the behaviour of both traps and incomplete ionization. The findings demonstrate that incomplete ionization and interface traps significantly affect TFET performance, with Gaussian traps posing a greater challenge due to their broader energy distribution. The study provides valuable insights for optimizing TFET designs by accounting for these non-idealities, which can improve device reliability and performance in practical applications. In conclusion, the research contributes to the understanding of incomplete ionization in the presence of interface traps and its implications for TFETs, offering guidance for the development of more efficient and reliable transistor designs.