Impact of the Endurance Measurement Methodology on Ferroelectric Field Effect Transistor Under the Capacitive Nondestructive Read

Abstract

In this article, the impact of the measurement delay and connection to the body contact on the reliability of the ferroelectric field effect transistor (FeFET) under the capacitive nondestructive read mode is studied. Specifically, the endurance characteristics of the FeFET’s gate-to-source/drain capacitance are analyzed. The study is performed on 28-nm bulk Si FeFET technology, with body contact either grounded or floating. We find that the FeFET device exhibits an erase after program delay, where as the number of pulses during the bipolar stress increases, the ferroelectric switching of the FeFET reduces. During the memory window (MW) evaluation (after the bipolar stress), the system setup delays are longer than the erase after program delay in the actual operation. Hence, the ferroelectric switching is restored showing a full MW. The results indicate that the presence of this erase after program delay imposes a minimum stress frequency on the device, which in turn increases the measurement time. Furthermore, the result points toward the need to re-evaluate the standard endurance measurement practice.