Fluorine-Treated Top-Gate InAlZnO TFT for 2T0C DRAM With Long Data Retention at Vhold = 0 V

Abstract

Top-gate InAlZnO (IAZO) thin-film transistors (TFTs) fabricated with plasma-enhanced atomic layer deposition (PEALD) are investigated for 2T0C DRAM cells. By using Ar plasma to treat the source/drain (S/D) region, significant improvement in S/D contact properties is obtained and the on-state current ( ${I}_{\text {on}}\text {)}$ is boosted by about three orders of magnitude. Furthermore, we employ a fluorine-treated method to modulate the threshold voltage ( ${V}_{\text {th}}\text {)}$ and ${I}_{\text {on}}$ of the top-gate IAZO TFT. By optimizing the fluorine-treatment parameters for the IAZO channel, the resultant TFT exhibits a positive ${V}_{\text {th}}$ of 0.64 V, a small subthreshold swing (SS) of 74 mV/dec, a negligible clockwise hysteresis window of ~6 mV, an excellent uniformity ( ${V}_{\text {th}}$ variation <0.2> ${I}_{\text {on}}$ increase of more than 50% as compared with the untreated device. Negative bias stability (NBS) of the F-treated IAZO TFT is significantly improved, showing a negligible ${V}_{\text {th}}$ shift of −0.005 V after 60 min stress at −3 MV cm−1. Moreover, 2T0C DRAM cells based on the F-treated top-gate IAZO TFTs are fabricated, demonstrating a long retention time of >1 ks at zero hold voltage ( ${V}_{\text {hold}}\text {)}$ , and an excellent endurance property over $10^{{10}}$ cycles. Finally, the top-gate IAZO TFTs and 2T0C DRAM cells with downscaled channel length are further investigated, demonstrating an ${I}_{\text {on}}$ of $3.2~\mu $ A/ $\mu $ m and a retention time of 80 s at ${V}_{\text {hold}} = 0$ V. These results indicate that the top-gate IAZO TFTs have great potential for memory applications with extremely low static power consumption.