Trench-Gate Bipolar Transistor With Partially Buried Carrier Storage Layer for Enhanced Blocking and Switching Characteristics

IF 2.9 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Electron Devices Pub Date : 2025-03-28 DOI:10.1109/TED.2025.3552365

Changhao Wang;Jianbin Guo;Jingjing Tan;Qingqing Sun;David Wei Zhang;Hao Zhu

{"title":"Trench-Gate Bipolar Transistor With Partially Buried Carrier Storage Layer for Enhanced Blocking and Switching Characteristics","authors":"Changhao Wang;Jianbin Guo;Jingjing Tan;Qingqing Sun;David Wei Zhang;Hao Zhu","doi":"10.1109/TED.2025.3552365","DOIUrl":null,"url":null,"abstract":"In this work, an insulated gate bipolar transistor (IGBT) with partially buried carrier storage (PBCS) layer is proposed and studied. By embedding the highly doped carrier storage (CS) layer into the base region, the electric field intensity near the CS layer is reduced, thus avoiding the breakdown voltage (BV) drop that occurs in conventional carrier stored trench-gate bipolar transistor (CSTBT) devices. The simulation results suggest that the doping concentration of the CS layer in the proposed PBCS device is increased to <inline-formula> <tex-math>$6 \\times 10^{{17}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{3}}$ </tex-math></inline-formula>, and the <sc>on</small>-state voltage (<inline-formula> <tex-math>${V}_{\\text {ON}}$ </tex-math></inline-formula>) is lowered by 0.1 V without degrading the BV. At the same time, the Miller capacitance is reduced by 39% due to the lower silicon doping concentration at the bottom of the trench gate. Besides, by combining the CS layer region with additional hole-extracting channels, the device switching characteristics are significantly improved with 15% and 13% reduction in turn-on and turn-off loss, respectively. The proposed PBCS device is fully compatible with the existing IGBT manufacturing process, which paves promising pathways for future high-performance power electronic device applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2480-2485"},"PeriodicalIF":2.9000,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10945454/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

In this work, an insulated gate bipolar transistor (IGBT) with partially buried carrier storage (PBCS) layer is proposed and studied. By embedding the highly doped carrier storage (CS) layer into the base region, the electric field intensity near the CS layer is reduced, thus avoiding the breakdown voltage (BV) drop that occurs in conventional carrier stored trench-gate bipolar transistor (CSTBT) devices. The simulation results suggest that the doping concentration of the CS layer in the proposed PBCS device is increased to

$6 \times 10^{{17}}$

${}^{-{3}}$

, and the on-state voltage (

${V}_{\text {ON}}$

) is lowered by 0.1 V without degrading the BV. At the same time, the Miller capacitance is reduced by 39% due to the lower silicon doping concentration at the bottom of the trench gate. Besides, by combining the CS layer region with additional hole-extracting channels, the device switching characteristics are significantly improved with 15% and 13% reduction in turn-on and turn-off loss, respectively. The proposed PBCS device is fully compatible with the existing IGBT manufacturing process, which paves promising pathways for future high-performance power electronic device applications.

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具有部分埋置载流子存储层的沟槽栅双极晶体管，用于增强阻塞和开关特性

本文提出并研究了一种具有部分埋置载流子存储层（PBCS）的绝缘栅双极晶体管（IGBT）。通过将高掺杂的载流子存储层（CS）嵌入基极区，降低了CS层附近的电场强度，从而避免了传统载流子存储沟栅双极晶体管（CSTBT）器件中出现的击穿电压（BV）下降。仿真结果表明，所设计的PBCS器件中CS层的掺杂浓度提高到$6 \ × 10^{{17}}$ cm ${}^{-{3}}$，导通电压（${V}_{\text {ON}}$）降低了0.1 V，但未降低BV。同时，由于沟槽栅底部硅掺杂浓度较低，米勒电容降低了39%。此外，通过将CS层区域与额外的孔提取通道相结合，器件的开关特性得到了显著改善，导通和关断损耗分别降低了15%和13%。提出的PBCS器件与现有的IGBT制造工艺完全兼容，为未来高性能电力电子器件的应用铺平了有希望的道路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Electron Devices 工程技术-工程：电子与电气

CiteScore

5.80

自引率

16.10%

发文量

937

审稿时长

3.8 months

期刊介绍： IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.