Comprehensive Investigation of Bias Stress-Induced Instabilities in Highly Scaled ZnO FeFETs: Impact of Channel Thickness, Channel Length, and Switching Cycles

Abstract

We present a comprehensive study of instabilities induced by positive and negative bias stress (PBS/NBS) in zinc oxide (ZnO) ferroelectric field-effect transistors (FeFETs), focusing on the dependence of threshold voltage ( ${V} _{\text {TH}}$ ) and memory window (MW) dynamics on channel thickness ( ${T} _{\text {CH}}$ ), channel length ( ${L} _{\text {CH}}$ ), and switching cycles. Based on Zr-doped HfO2 (HZO) and by optimizing ${T} _{\text {CH}}$ and scaling ${L} _{\text {CH}}$ down to 45 nm, high-performance ZnO FeFETs with an HZO-Al2O3–HZO ferroelectric (Fe) stack and an atomic layer deposition (ALD)-deposited channel are realized, achieving a large MW of 3.0 V, robust retention, and high endurance exceeding 108 cycles. Bias stress investigations reveal several key findings. First, devices with thinner ${T} _{\text {CH}}$ exhibit higher ${V} _{\text {TH}}$ susceptibility under PBS and NBS, which attributed to stronger electron trapping effects and the generation of more disorder state (DS) O2- defects, respectively. Thanks to the strengthened effect of NBS-enhanced erasing, thinner ${T} _{\text {CH}}$ results in better MW tolerance during NBS, thus partially offsetting the MW degradation due to polarization pinning. Second, this NBS-enhanced erasing effect is particularly pronounced in short-channel devices ( ${L} _{\text {CH}} = 45$ nm), even leading to an increase in MW. In contrast, during PBS, ${L} _{\text {CH}}$ has little impact on ${V} _{\text {TH}}$ and MW instabilities. Finally, it is observed that the degraded MW in heavily cycled devices can be slightly recovered after NBS.