{"title":"Extremely High ESD Failure Voltage of RESURF LDMOS Devices for ESD Resilient Driver Applications","authors":"Aakanksha Mishra;M. Monishmurali;B. Sampath Kumar;Shaik Ahamed Suzaad;Shubham Kumar;Kiran Pote Sanjay;Amit Kumar Singh;Avinash Singh;Ankur Gupta;Mayank Shrivastava","doi":"10.1109/TED.2025.3556114","DOIUrl":null,"url":null,"abstract":"This work reports an extremely high ESD failure voltage in the transmission line pulse (TLP) characteristics of the laterally diffused metal-oxide-semiconductor (LDMOS) devices, while investigating a correlation between the critical voltage and filament formation. A high failure voltage enables an additional immunity to ESD damage by providing extra protection against the overvoltage stress in high-voltage (HV) I/O applications. The ESD behavior of LDMOS devices in the presence of reduced surface field (RESURF)-implant in the drift region is investigated in detail. Furthermore, an approach to drift region design and electric field engineering that affects this high failure voltage in RESURF LDMOS devices is discussed, using measurement and 3-D TCAD simulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2187-2194"},"PeriodicalIF":2.9000,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10959327/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This work reports an extremely high ESD failure voltage in the transmission line pulse (TLP) characteristics of the laterally diffused metal-oxide-semiconductor (LDMOS) devices, while investigating a correlation between the critical voltage and filament formation. A high failure voltage enables an additional immunity to ESD damage by providing extra protection against the overvoltage stress in high-voltage (HV) I/O applications. The ESD behavior of LDMOS devices in the presence of reduced surface field (RESURF)-implant in the drift region is investigated in detail. Furthermore, an approach to drift region design and electric field engineering that affects this high failure voltage in RESURF LDMOS devices is discussed, using measurement and 3-D TCAD simulation.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.