Ultra-Long Disturb-Free Read Operation With Low Resistance Drift in Phase Change Memory

Abstract

Compute-in-memory requires long endurance in reading of memory device orders of magnitude higher than writing. Variations in resistance of memory cells caused by read disturbance is a critical challenge for neural networks applications of emerging memory technology. Current generated by read voltage causes localized heating in the phase change memory (PCM) cell, which results in structural displacement of active phase change volume and thus appreciable variation in cell resistance. In this work, the effects of reading on both high and low resistance states (HRS and LRS) of PCM after various writing cycles are investigated. A disturb-free read scheme is demonstrated up to 1012 read cycles (~28 h) on the memory cells that experienced 108 write cycles both at $27~^{\circ }$ C and $85~^{\circ }$ C. The reduced resistance drift by increasing the read voltage up to 0.5 V is observed which further improves the speed and accuracy of reading. This work shows that carbon-doped Ge2Sb2Te5-based PCM is a promising candidate for compute-in-memory application that requires enormous reading with high-precision.