Post Work-Function Metal Annealing Induced Significant Reliability Improvement for DDDPMOS With Dual SiO₂ Layers and Metal Gate

IF 2.9 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Electron Devices Pub Date : 2025-04-03 DOI:10.1109/TED.2025.3554133

Cheng-Hao Liang;Hang Li;Ran Bi;Han-Wen Ding;Yu-Long Jiang

{"title":"Post Work-Function Metal Annealing Induced Significant Reliability Improvement for DDDPMOS With Dual SiO₂ Layers and Metal Gate","authors":"Cheng-Hao Liang;Hang Li;Ran Bi;Han-Wen Ding;Yu-Long Jiang","doi":"10.1109/TED.2025.3554133","DOIUrl":null,"url":null,"abstract":"In this work, the effect of post work-function metal spike annealing (PWA) in N2 on the reliability of the high-voltage (HV) double-diffused drain PMOSFET (DDDPMOS) with dual SiO2 layers and metal gate (MG) is investigated. Compared to the usually employed post metal annealing (PMA), the proposed PWA is revealed to allow more nitrogen to diffuse into the in-situ steam generation (ISSG) oxide layer and eliminate oxygen vacancies. Hence, ~1500% negative bias thermal instability (NBTI) lifetime improvement for DDDPMOS is demonstrated. Slight NBTI characteristic improvement without <inline-formula> <tex-math>${I}_{\\scriptstyle\\mathrm {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{\\scriptstyle\\mathrm {OFF}}$ </tex-math></inline-formula> performance degradation is also observed for the low-voltage (LV) pMOS integrated within the same die, which suggests that the PWA process can be used as a substitute for PMA and a novel solution to improve reliability for display driver chip fabrication using high-k/MG (HK/MG) technology with the effective integration of core devices with very small feature sizes and HV devices with large feature sizes and thick oxide in the same die.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2173-2178"},"PeriodicalIF":2.9000,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10948320/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

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Abstract

In this work, the effect of post work-function metal spike annealing (PWA) in N2 on the reliability of the high-voltage (HV) double-diffused drain PMOSFET (DDDPMOS) with dual SiO2 layers and metal gate (MG) is investigated. Compared to the usually employed post metal annealing (PMA), the proposed PWA is revealed to allow more nitrogen to diffuse into the in-situ steam generation (ISSG) oxide layer and eliminate oxygen vacancies. Hence, ~1500% negative bias thermal instability (NBTI) lifetime improvement for DDDPMOS is demonstrated. Slight NBTI characteristic improvement without

${I}_{\scriptstyle\mathrm {ON}}$

${I}_{\scriptstyle\mathrm {OFF}}$

performance degradation is also observed for the low-voltage (LV) pMOS integrated within the same die, which suggests that the PWA process can be used as a substitute for PMA and a novel solution to improve reliability for display driver chip fabrication using high-k/MG (HK/MG) technology with the effective integration of core devices with very small feature sizes and HV devices with large feature sizes and thick oxide in the same die.

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后工作功能金属退火可显著提高双sio2层和金属栅极DDDPMOS的可靠性

本文研究了N2中工作功能后金属尖峰退火（PWA）对具有双SiO2层和金属栅极（MG）的高压双扩散漏极PMOSFET （DDDPMOS）可靠性的影响。与通常采用的金属后退火（PMA）相比，PWA允许更多的氮扩散到原位蒸汽生成（ISSG）氧化层并消除氧空位。因此，证明了DDDPMOS的负偏置热不稳定性（NBTI）寿命提高了~1500%。在没有${I}_{\scriptstyle\mathrm {ON}}$ / ${I}_{\scriptstyle\mathrm {OFF}}$的情况下，对于集成在同一芯片内的低压（LV） pMOS，也观察到轻微的NBTI特性改善。这表明PWA工艺可以作为PMA的替代品，并通过将具有非常小特征尺寸的核心器件和具有大特征尺寸和厚氧化物的HV器件有效集成在同一模具中，为使用高k/MG （HK/MG）技术提高显示驱动芯片制造可靠性提供了一种新颖的解决方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Electron Devices 工程技术-工程：电子与电气

CiteScore

5.80

自引率

16.10%

发文量

937

审稿时长

3.8 months

期刊介绍： IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.