{"title":"Signal Integrity Analysis of Tapered Through Packaging Multibit Glass Vias Using Exponential Matrix–Rational Approximation Technique","authors":"Ajay Kumar;Rohit Dhiman","doi":"10.1109/TCPMT.2025.3553362","DOIUrl":null,"url":null,"abstract":"In this article, we develop a wideband scalable analytical model of tapered through packaging differential multibit vias (TP-DMVs) with pads in glass interposer by developing an exponential matrix-rational approximation (EM-RA) technique. An electrical <italic>RLGC</i> model, which also includes the skin effect, is proposed as a function of geometric parameters of tapered through glass vias. The scalability of <italic>RLGC</i> equivalent circuit is verified in terms of <italic>S</i>-parameters against the 3-D electromagnetic (EM) high-frequency structure simulator (HFSS) up to 100 GHz, for a wide variety of tapered TP-DMV dimensions, including the effects of slope angle and aspect ratio. The maximum reduction in capacitance and conductance values of tapered TP-DMVs with a slope angle is ~75%, while the maximum increase in resistance and inductance value is ~93%. The signal integrity parameters, such as crosstalk, time to reach peak crosstalk, and propagation delay under the influence of surface roughness (SR) and temperature variations, are computed using the EM-RA technique and industry-level simulator SPICE. The variations include temperature and glass SR ranges from (300–500 K) and (150–<inline-formula> <tex-math>$1.5~\\mu $ </tex-math></inline-formula>m). The comparison shows excellent conformity with less than 1% error. Through the proposed EM-RA technique and Nyquist stability criterion, it is shown that, by increasing the slope angle and pitch, the tapered TP-DMVs become relatively more stable.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1014-1024"},"PeriodicalIF":3.0000,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10935301/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this article, we develop a wideband scalable analytical model of tapered through packaging differential multibit vias (TP-DMVs) with pads in glass interposer by developing an exponential matrix-rational approximation (EM-RA) technique. An electrical RLGC model, which also includes the skin effect, is proposed as a function of geometric parameters of tapered through glass vias. The scalability of RLGC equivalent circuit is verified in terms of S-parameters against the 3-D electromagnetic (EM) high-frequency structure simulator (HFSS) up to 100 GHz, for a wide variety of tapered TP-DMV dimensions, including the effects of slope angle and aspect ratio. The maximum reduction in capacitance and conductance values of tapered TP-DMVs with a slope angle is ~75%, while the maximum increase in resistance and inductance value is ~93%. The signal integrity parameters, such as crosstalk, time to reach peak crosstalk, and propagation delay under the influence of surface roughness (SR) and temperature variations, are computed using the EM-RA technique and industry-level simulator SPICE. The variations include temperature and glass SR ranges from (300–500 K) and (150–$1.5~\mu $ m). The comparison shows excellent conformity with less than 1% error. Through the proposed EM-RA technique and Nyquist stability criterion, it is shown that, by increasing the slope angle and pitch, the tapered TP-DMVs become relatively more stable.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.