Implementation and investigation of high voltage CMOS device in advanced Sub-90 nm node processes

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-04-28 DOI:10.1016/j.sse.2025.109142

Xin Huang , Yintong Zhang , Zhaozhao Xu , Ziquan Fang , Donghua Liu , Wensheng Qian

引用次数: 0

Abstract

The continuous scaling of MOSFET devices exacerbates short-channel effects (SCEs), such as hot-carrier injection (HCI) and threshold voltage roll-off, thereby compromising electrical performance. While lightly doped drain (LDD) processes are widely adopted in modern CMOS fabrication, conventional methods struggle to maintain performance at advanced technology nodes. This work proposes a novel high-energy LDD technology that overcomes these limitations without introducing additional fabrication complexity. Through rigorous TCAD simulations, the proposed process demonstrates enhanced device stability and improved electrical characteristics, including lower breakdown voltage variation, better threshold voltage control, and improved on/off current ratios. Benchmarked against conventional non-self-aligned (NSA) and self-aligned (SA) LDD processes, this technology offers a viable pathway for next-generation semiconductor scaling.

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先进sub - 90nm节点制程中高压CMOS器件的实现与研究

MOSFET器件的连续缩放加剧了短通道效应（SCEs），例如热载流子注入（HCI）和阈值电压滚降，从而影响了电气性能。虽然轻掺杂漏极（LDD）工艺在现代CMOS制造中被广泛采用，但传统方法难以在先进技术节点上保持性能。这项工作提出了一种新的高能LDD技术，克服了这些限制，而不引入额外的制造复杂性。通过严格的TCAD仿真，所提出的工艺证明了增强的器件稳定性和改善的电气特性，包括更低的击穿电压变化，更好的阈值电压控制和改进的通/关电流比。与传统的非自对准（NSA）和自对准（SA） LDD工艺相比，该技术为下一代半导体缩放提供了一条可行的途径。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.