A 56-Gb/s DAC/ADC-Based Multicarrier Transceiver With TX Polar DSP and RX MIMO-DSP for >40-dB Loss Channel

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Srujan Kumar Kaile;Julian Camilo Gomez Diaz;Yuanming Zhu;Il-Min Yi;Tong Liu;Sebastian Hoyos;Samuel Palermo
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引用次数: 0

Abstract

This letter presents a digital-to-analog-converter/analog-to-digital converter (DAC/ADC)-based multicarrier transceiver fabricated in a 22-nm FinFET technology. The multicarrier signaling scheme utilizes orthogonally spaced carriers for spectral efficient band spacing and exhibit jitter robustness compared to conventional baseband pulse amplitude-based signaling. The transmitter has a polar digital signal processor (DSP) to generate the equalized codes driving the 7-b phase DACs, and 7-b amplitude DACs with 2-b predistortion to yield 1.2-Vppd swing. The multicarrier receiver front-end ADC outputs are equalized with a MIMO DSP backend to compensate for the intersymbol interference and interchannel interference. The measured transceiver at 56 Gb/s through a 40.8-dB loss at 14-GHz channel showed a jitter tolerance of up to 1.21 psrms at BER $\lt 10{^{-}4 }$ with 7.82-pJ/bit power efficiency.
一种56gb /s基于DAC/ adc的多载波收发器,具有TX极性DSP和RX MIMO-DSP,适用于>40-dB损耗通道
本文介绍了一种采用22nm FinFET技术制造的基于数模转换器/模数转换器(DAC/ADC)的多载波收发器。与传统的基于基带脉冲幅度的信令相比,多载波信令方案利用正交间隔载波实现频谱高效频带间隔,并表现出抖动鲁棒性。发射机具有一个极性数字信号处理器(DSP),用于生成驱动7b相位dac和7b幅度dac的均衡代码,其预失真为2b,产生1.2 vppd摆幅。多载波接收机前端ADC输出由MIMO DSP后端均衡,以补偿码间干扰和信道间干扰。在14ghz信道下,通过40.8 db损耗,以56gb /s速率测量的收发器在BER $\lt 10{^{-}4}$下的抖动容忍度高达1.21 psrms,功率效率为7.82 pj /bit。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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