{"title":"Linear Fine-Tuning VFB and Improved Interface via Novel Al₂O₃ Atomic in-situ Dipole Buffer Layer (DBL) in ALD La₂O₃ Dipole-First Stack","authors":"Yanzhao Wei;Jiaxin Yao;Yu Wang;Qingzhu Zhang;Jianfeng Gao;Xiaolei Wang;Jun Luo;Huaxiang Yin","doi":"10.1109/LED.2025.3549003","DOIUrl":null,"url":null,"abstract":"In this letter, a novel Al2O3 atomic in-situ dipole buffer layer (DBL) technique is proposed for achieving VFB linear fine-tunability and interface improvement in La2O3 dipole-first gate stack. 10 VFB levels with minimum 9 mV linear fine-tuning step in 400 mV range are achieved by manipulating sub-5-Å Al2O3 between SiO2 interfacial layer (IL) and La2O3 dipole layer in metal-oxide-semiconductor capacitors (MOSCAPs). Furthermore, the Si/SiO2 interface is improved with more than 60.3% interface trap density (Dit) decrease by suppressing La-Si interdiffusion with Al-DBL. A mechanism of La-dipole fine-tuning is proposed and indicates that the Al-DBL is one of the promising techniques for multi-VT integration in future NS GAA-FETs.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"825-828"},"PeriodicalIF":4.1000,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10916698/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this letter, a novel Al2O3 atomic in-situ dipole buffer layer (DBL) technique is proposed for achieving VFB linear fine-tunability and interface improvement in La2O3 dipole-first gate stack. 10 VFB levels with minimum 9 mV linear fine-tuning step in 400 mV range are achieved by manipulating sub-5-Å Al2O3 between SiO2 interfacial layer (IL) and La2O3 dipole layer in metal-oxide-semiconductor capacitors (MOSCAPs). Furthermore, the Si/SiO2 interface is improved with more than 60.3% interface trap density (Dit) decrease by suppressing La-Si interdiffusion with Al-DBL. A mechanism of La-dipole fine-tuning is proposed and indicates that the Al-DBL is one of the promising techniques for multi-VT integration in future NS GAA-FETs.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.