High-Performance Two-Tier FinFETs With Low-Temperature (≤ 500 °C) Silicide Dopant Segregation Schottky S-D for M3D Circuits

IF 4.1 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Electron Device Letters Pub Date : 2025-03-24 DOI:10.1109/LED.2025.3553873

Feixiong Wang;Yadong Zhang;Yunjiao Bao;Shuang Liu;Xuexiang Zhang;Shujuan Mao;Mingzheng Ding;Jinbiao Liu;Jiaxin Yao;Qingzhu Zhang;Huaxiang Yin

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引用次数: 0

Abstract

In this work, 2-tier Monolithic 3-Dimentional (M3D) integrated FinFETs and circuits are fabricated based on a low-temperature (

$\le 500~^{\circ }$

C) silicide dopant segregation Schottky Source/Drian (SDSS S-D) technology. By forming NiPt silicide followed by B/P implantation and optimizing annealing on top-tier fins, a sharpened Schottky Barrier of the silicide and a high dopant segregation concentration of the impurities are obtained in the improved silicide S-D with maximum process temperature below

$500~^{\circ }$

C. As a result, Low-T 2-tier M3D FinFETs are obtained with I

${}_{\text {ON}}= 646.4~\mu $

$\mu $

m for PMOS and I

${}_{\text {ON}} = 450.6~\mu $

$\mu $

m for NMOS at L

${}_{\text {G}}=500$

nm and a record I

${}_{\text {ON}}=1.84$

mA/

$\mu $

m is achieved for PMOS at L

${}_{\text {G}} =25$

nm under normalized footprint. Furthermore, M3D inverter, ring oscillators, as well as 6T SRAM with this technique are demonstrated, which is promising to provide an effective and low-cost method to achieve low-temperature high- performance silicon circuits in M3D applications.

查看原文本刊更多论文

高性能两层finfet低温（≤500°C）硅化掺杂偏析肖特基S-D用于M3D电路

在这项工作中，基于低温（$\le 500~^{\circ }$ C）硅化掺杂剂偏析肖特基源/德里安（SDSS S-D）技术制造了两层单片三维（M3D）集成finfet和电路。通过形成NiPt硅化物，再进行B/P注入，优化顶层翅片的退火，在最高工艺温度低于$500~^{\circ }$ c的改进硅化物S-D中获得了尖锐的硅化物肖特基势垒和较高的杂质掺杂偏析浓度。在L ${}_{\text {G}}=500$ nm处，PMOS和NMOS分别获得了1 ${}_{\text {ON}}= 646.4~\mu $ A/ $\mu $ m和1 ${}_{\text {ON}} = 450.6~\mu $ A/ $\mu $ m的低t 2层M3D finfet， PMOS在L ${}_{\text {G}} =25$ nm处实现了1 ${}_{\text {ON}}=1.84$ mA/ $\mu $ m的记录。此外，M3D逆变器、环形振荡器、6T SRAM等器件均采用了该技术，有望为实现M3D应用中的低温高性能硅电路提供一种有效、低成本的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Electron Device Letters 工程技术-工程：电子与电气

CiteScore

8.20

自引率

10.20%

发文量

551

审稿时长

1.4 months

期刊介绍： IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.