On the Enhanced p-Type Performance of Back-Gated WS2 Devices

Abstract

In this work, a scalable technique is presented for the direct growth of tungsten disulfide (WS₂) utilized in back-gated field-effect transistors (FETs), demonstrating robust and persistent p-type behavior across diverse conditions. Notably, this p-type behavior is consistently observed regardless of the metal contacts, semiconductor thickness, or ambient conditions, and remains stable even after high-vacuum and high-temperature annealing. Electrical characterization reveals negligible Fermi-level pinning at the conduction band edge, with minimal Schottky barrier heights for hole carriers below 180 mV and a well-defined thermionic transport regime. The devices exhibit field-effect mobilities with a clear back-gate dependence, reaching values up to 0.1 cm²V⁻¹s⁻¹. Temperature-dependent transport analysis indicates that charge carrier mobility is predominantly limited by impurity scattering and Coulomb interactions. First-principles simulations corroborate that the persistent p-type behavior could be driven by the presence of tungsten vacancies or WO₃ oxide species. This study highlights the potential of WS₂ for scalable integration into advanced p-type electronic devices and provides critical insights into the intrinsic mechanisms governing its charge transport properties.