F.E. Bergamaschi , J.A. Matos , M. de Souza , S. Barraud , M. Cassé , O. Faynot , M.A. Pavanello
{"title":"Operation of junctionless nanowire transistors down to 4.2 Kelvin","authors":"F.E. Bergamaschi , J.A. Matos , M. de Souza , S. Barraud , M. Cassé , O. Faynot , M.A. Pavanello","doi":"10.1016/j.sse.2025.109133","DOIUrl":null,"url":null,"abstract":"<div><div>In this work, an experimental characterization of SOI junctionless nanowire transistors operating in liquid helium temperature is conducted. DC measurements are performed in a temperature range from 300 K down to 4.2 K in devices with variable geometrical dimensions, namely the gate length and the fin width. Different electrical parameters are analyzed, such as the threshold voltage, the subthreshold slope, the low-field mobility, and the drain-induced barrier lowering (DIBL). The temperature reduction helps partially suppress short-channel effects, leading to improvement in these parameters while preserving good electrostatic control, even for highly scaled channel lengths.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109133"},"PeriodicalIF":1.4000,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125000784","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, an experimental characterization of SOI junctionless nanowire transistors operating in liquid helium temperature is conducted. DC measurements are performed in a temperature range from 300 K down to 4.2 K in devices with variable geometrical dimensions, namely the gate length and the fin width. Different electrical parameters are analyzed, such as the threshold voltage, the subthreshold slope, the low-field mobility, and the drain-induced barrier lowering (DIBL). The temperature reduction helps partially suppress short-channel effects, leading to improvement in these parameters while preserving good electrostatic control, even for highly scaled channel lengths.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.