Evaluation of the effective channel length of Junctionless nanowire transistors with different drain bias through the gate capacitance

Abstract

This paper analyzes through 3D numerical simulations the effective channel length (L_EFF) of Junctionless Nanowire Transistors (JNT) through the gate capacitance (C_GG) of the devices for different drain-to-source voltages (V_DS) and compares the results with a theoretical approach. In this case, there is a phenomenon of intersection through the C_GG curves for high V_DS bias (between 0.5 V and 1 V) that indicates the pinch-off regime of the JNTs. The L_EFF extraction has been done from the extrapolation of the gate capacitance in the pinch-off regime as a function of the device’s channel length (L_MASK), for different L_MASK and source and drain lengths (L_SD) for structures with lateral spacer and different doping concentrations, showing that L_EEF increases ∼ 6 nm and presents a relationship with V_DS bias and doping concentration. Finally, one comparison with the theoretical equation was done, showing that the method is a good way to extract or even estimate the effective channel length of the experimental devices.