Improvement of bonding interface in electroless copper-plated joints using a high copper concentration copper–quadrol complex solution

Abstract

In the semiconductor industry, scaling down high-density, 3D-stacked interconnections is critical for enhancing efficiency and performance. However, this miniaturization introduces challenges that require innovative chip packaging solutions. A previous study developed a chip packaging process using a high copper concentration and high plating rate electroless copper plating solution. This process offers advantages such as low temperature, short processing time, and a pressureless nature, which can address the problems encountered by other packaging processes. However, this process is challenged by the presence of voids at the bonded interface. Therefore, this study builds on previous work by exploring two strategies for minimizing void formation in electroless copper-plated joints: reducing pillar size and altering pillar geometry. A copper–quadrol complex solution was used at 35 °C for 7 min to bond the copper pillar joints. The experiments showed that reducing the effective pillar diameter significantly increased the bonded area percentage, with a notable 97 % bonded area at a 3.5 μm effective pillar diameter. Additionally, the dome-shaped pillars demonstrated superior performance by effectively eliminating large voids compared with flat-topped pillars. These findings indicate that void-free bonding can be achieved by strategically adjusting both the geometry and size of the pillars. Moreover, this work not only provides the semiconductor industry with methods to reduce void size but also demonstrates a potential process to address the critical challenges posed by miniaturization in chip packaging.