Automatic Test and Array Crosstalk Suppression Scheme for 3D-ICs With Inductively Coupled Interconnections

Abstract

Inductively coupled interconnection (ICI) is a wireless interchip interconnect technology for 3D-ICs, which offers cost savings and enhanced flexibility compared to through-silicon via (TSV). However, ICI presents unique key challenges, including high power consumption, reliability issues, and the complexity of wire bonding during the stacking process. To overcome these challenges, we propose a new packaging process, chip edge connection (CEC), and self-sorting and power-tuning circuits. We also propose an array crosstalk suppression (ACS) strategy. We showed the designed chip in a 180-nm CMOS process. The results show that the CEC process can establish a conductive channel at the chip edge. The self-sorting circuit can provide chip IDs without wire bonding. For four-layer stacked chips with a 50% single-layer misalignment, the power-tuning circuit reduces power consumption by 20.98%. Furthermore, the ACS scheme reduces the bit error rate (BER) to between $1\times 10^{-10}$ and $1\times 10^{-12}$ at average misalignment levels of 10%–50% in the ICI channel.