{"title":"High-Efficiency Extraction Method for Thermal Network Model of Advanced Electronic Packages","authors":"Ian Hu;Yu-Chih Kuo;Tian-Shiang Yang","doi":"10.1109/TCPMT.2025.3547229","DOIUrl":null,"url":null,"abstract":"To reduce the number of grids in numerical computations that involve multiple length scales, a compact thermal model of an electronic package is widely used for electronic system thermal design. This study was conducted according to development of libraries of physical models for an integrated design environment (DELPHI) procedure and extended to dual-chip application. A flip-chip chip-scale package (FCCSP) containing a single or dual chip was chosen as the test vehicle. A domain-knowledge-assisted sequential least-squares programming (SLSQP) technique is used to minimize the objective function; meanwhile, the genetic algorithm (GA) technique is used for comparison. This study examines how to use domain knowledge on initial condition settings when using SLSQP and how to increase spatial resolution to improve the network models effectively. It is found that using calculated 1-D thermal resistances as the initial estimates of the critical thermal resistance parameters can increase the accuracy of the network model training by SLSQP, which has accuracy similar to GA and much better computational efficiency. This study also demonstrates that the network model can be improved by systematically increasing its spatial resolution of the main heat dissipation path based on the errors observed in primary attempts, which has more benefits than increasing the spatial resolution of the surface having a larger temperature difference.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"716-724"},"PeriodicalIF":2.3000,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10908880/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
To reduce the number of grids in numerical computations that involve multiple length scales, a compact thermal model of an electronic package is widely used for electronic system thermal design. This study was conducted according to development of libraries of physical models for an integrated design environment (DELPHI) procedure and extended to dual-chip application. A flip-chip chip-scale package (FCCSP) containing a single or dual chip was chosen as the test vehicle. A domain-knowledge-assisted sequential least-squares programming (SLSQP) technique is used to minimize the objective function; meanwhile, the genetic algorithm (GA) technique is used for comparison. This study examines how to use domain knowledge on initial condition settings when using SLSQP and how to increase spatial resolution to improve the network models effectively. It is found that using calculated 1-D thermal resistances as the initial estimates of the critical thermal resistance parameters can increase the accuracy of the network model training by SLSQP, which has accuracy similar to GA and much better computational efficiency. This study also demonstrates that the network model can be improved by systematically increasing its spatial resolution of the main heat dissipation path based on the errors observed in primary attempts, which has more benefits than increasing the spatial resolution of the surface having a larger temperature difference.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.