Impact on Reliability of Microvoids and β-Sn Anisotropy in Flip-Chip Bumps

Abstract

The formation of small voids can occur in solder-based flip chip joints during the assembly process and a concern for certain applications that involve high electrical and thermal flux across the flip chip and also impact on electromigration (EM) in the joint. In this study, the impact of microvoids within flip-chip interconnections using Cu pillar bumps on EM resistivity was investigated. These microvoids can significantly affect the reliability of interconnections. To explore this, we intentionally created large voids in the solder bumps and measured the resulting differences in EM resistivity. The EM tests were conducted under specific conditions: at 150 °C and with a current density of 40 kA/cm2. Electron flow occurred in two directions—either from the Cu pad on the substrate side to the Cu pillar side (forward direction) or from the Cu pillar side to the substrate side (reverse direction). Surprisingly, the EM lifetime of interconnects with large voids was approximately 0.4 times shorter than that of interconnects with few or no voids, regardless of the electron flow direction. Further analysis by the simulation of current density distribution revealed that the presence of a 10- $\mu $ m-diameter void near the cathode interface led to a 1.5-fold increase in current density. Interestingly, this increase aligned well with Black’s empirical formula, which describes the relationship between EM lifetime and current density. In addition, the combination of c-axis of beta-Sn grain aligned with current direction around void at cathode interface, significantly accelerated EM test results.