Performance and reliability analysis of redistribution layers under interfacial crack

Abstract

The growing demand for high-density and high-performance semiconductor devices has accelerated the adoption of three-dimensional (3D) integration technologies, where redistribution Layer (RDL) structures play a critical role in signal routing and interconnect reliability. However, as the technology advances, it imposes significant stress on the RDL structure that can compromise its mechanical integrity and lead to cracks formation. Consequently, the likelihood of crack formation within these structures increases, and neglecting these issues can lead to severe problems, including reduced device performance and even permanent damage to the device. To address these confronting challenges, the study proposes an analytical modeling to analyze the influence of the RDL structure, considering interfacial cracks in both heating and cooling conditions. In this context, the result reveals a notable improvement in the crosstalk delay, with a reduction of 22.29 % observed when the minimum crack width of 0.18 μm under heating conditions approached the defect-free condition. A thorough validation of the analytical results demonstrates an excellent agreement with the electromagnetic (EM) result, for a negligible deviation of only 3.4 % observed in the scattering parameter. This close correspondence between the simulated and quantitative results lends solid support for the accuracy and reliability of the research findings. Additionally, the analysis highlighted that the crack under the cooling condition is significantly more susceptible to power delay product (PDP) than heating conditions, with a vulnerability of 7.19 % higher at a crack width of 0.18 μm. These findings provide valuable insight into the effects of interfacial cracks on the via performance and offer a robust foundation for ensuring high-density packages of semiconductors.