Substrate crosstalk characterization for optimized isolation in FDSOI

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-03-31 DOI:10.1016/j.sse.2025.109117

Talha Chohan , Zhixing Zhao , Luca Pirro , Loren Dombroske , Jacob Ong , Olaf Zimmerhackl , Steffen Lehmann , David Pritchard , Tao Xue , Jan Hoentschel

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引用次数: 0

Abstract

The coupling (crosstalk) between devices through substrate is a limiting factor for the highly integrated mixed-mode and high frequency circuits. Silicon–On–Insulator (SOI) wafer with buried oxide (BOX) inherits better low frequency isolation compared to bulk silicon. However, at higher frequencies the advantage subsides due to capacitive coupling. For the mixed mode applications, the abrupt signal switching in digital circuitry poses a detrimental effect on the noise-sensitive analog circuitry. This work studies the crosstalk isolation in commercial SOI resistivity substrate (∼1–100 Ω.cm) by deploying design-based approaches for crosstalk reduction. A clear advantage of SOI vs standard bulk is reported especially for low-frequency range. Substrate well variance with different types of junctions is studied and demonstrated to reduce noise isolation. Moreover, a novel guard-ring scheme deploying the combination of resistive and capacitive elements has shown to have improvement in the noise isolation for wide band applications compared to the individual elements.

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FDSOI中优化隔离的衬底串扰特性

器件间通过衬底的耦合（串扰）是高集成度混合模式和高频电路的一个限制因素。与体硅相比，具有埋藏氧化物（BOX）的绝缘体上硅（SOI）晶圆具有更好的低频隔离性能。然而，在更高的频率下，由于电容耦合，优势减弱。在混合模式应用中，数字电路中的信号突变会对噪声敏感的模拟电路产生不利影响。本工作通过部署基于设计的串扰减少方法，研究了商用SOI电阻率衬底（~ 1-100 Ω.cm）中的串扰隔离。SOI与标准批量相比有一个明显的优势，特别是在低频范围内。研究并证明了不同类型结的衬底井方差可以降低噪声隔离。此外，与单个元件相比，一种新型的保护环方案部署了电阻性和容性元件的组合，在宽带应用中具有更好的噪声隔离效果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.