Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong
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引用次数: 0

Abstract

This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18- $\mu $ m CMOS process.
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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