Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong
{"title":"Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure","authors":"Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong","doi":"10.1109/LSSC.2025.3551357","DOIUrl":null,"url":null,"abstract":"This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m CMOS process.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"73-76"},"PeriodicalIF":2.2000,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10927604/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-$\mu $ m CMOS process.