Comparison of electro-thermal-mechanical stress in SiC MOSFETs under several short-circuit types

Abstract

In this paper, the electro-thermal-mechanical stress of SiC MOSFETs under current-limited short circuit (CL-SC) conditions, as employed in DC solid-state power controllers (DC-SSPCs), is investigated. The low on-resistance and high operating junction temperature (T_J) characteristics of SiC MOSFETs make them ideal power devices for DC-SSPC applications. During the clearing of a short circuit fault, the short circuit current is limited to a lower value by the DC-SSPC for an extended duration before being cut off. This leads to an increase in T_J within the SiC MOSFET, which raises reliability concerns. Research on the short circuit (SC) reliability of SiC MOSFETs has predominantly focused on the electro-thermal-mechanical stress under SC conditions in high-frequency converters (HFCs). However, the electro-thermal-mechanical stress and aging mechanisms of SiC MOSFETs under CL-SC conditions remain unclear. In this paper, SPICE-based and FEM-based simulations are conducted to analyze the electro-thermal-mechanical stress of SiC MOSFETs under CL-SC for DC-SSPCs and SC for HFCs. Results indicate that bonding wire lift-off, edge delamination, and voids in the middle of the solder layer are more likely to occur under CL-SC conditions, differing from those observed in SC for HFCs. Experimental results are presented to validate the simulation findings, providing a valuable reference for evaluating the reliability of SiC MOSFETs in DC-SSPC applications.