Finding a Promising CMOS Inverter Architecture With Silicon Nanosheet for Future Technology Node

Abstract

In this work, we systematically explore the static and dynamic performance of silicon nanosheet (NSH)-based complementary metal-oxide–semiconductor (CMOS) inverters, including complementary field-effect transistor (CFET), forksheet (FSH), and standard stacked NSH (s-NSH) configurations, for the 5 nm and beyond technology node. The performance analysis of CMOS inverters is conducted using 3-D process simulations in fully calibrated technology computer-aided design (TCAD) simulation, which is based on the self-consistent solution of the Boltzmann transport equation and Poisson’s equation with quantum and mobility correction terms. Our findings reveal that the CFET inverter achieves remarkable advancements by offering around a 3.7% boost in operating frequency and around −3.7% reduction in power dissipation while decreasing the area footprint by approximately −60.8% compared with the s-NSH inverter for the 1-nm technology node. Although the FSH inverter slightly lags behind CFET in performance metrics, it still outperforms the s-NSH inverter by delivering an around 3% increment in the frequency at an equivalent power level and an area reduction of around −6.9%. Furthermore, CFET demonstrates superior resilience to process parameter variations, including doping fluctuation, oxide thickness, interface trap charges, and channel thickness. This robustness, combined with their compact design and excellent gate electrostatic control, enables CFET inverters to consistently outperform both FSH and s-NSH inverters across all evaluated technology nodes and design parameters. These advantages firmly establish the CFET inverter as the preferred choice for future ultrascale technology nodes and low-power logic applications.