Compact Modeling of Trap-Assisted Tunneling Current in 3-D NAND Flash Memory

IF 2.9 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Electron Devices Pub Date : 2025-02-19 DOI:10.1109/TED.2025.3541603

Hyungjun Jo;Hyungcheol Shin

引用次数: 0

Abstract

In this research, a compact model is proposed for trap-assisted tunneling (TAT) currents in 3-D NAND flash memory during erase/write (EW) cycling. Using the trap spectroscopy by charge injection and sensing (TSCIS) technique, the average trap density and trap energy level are extracted and applied in the TAT model. The compact model integrates band-to-trap tunneling (BT), trap-to-band tunneling (TB), and trap-to-trap tunneling (TTT) mechanisms. In BT and TTT, tunneling to trap occurs only when the trap energy level is aligned with or below the injection level. Modified tunneling equations are used to address misaligned trap energy levels in TTT. The compact model demonstrates good agreement with measurement data across various word-line (WL) voltages and cycling conditions.

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来源期刊

IEEE Transactions on Electron Devices 工程技术-工程：电子与电气

CiteScore

5.80

自引率

16.10%

发文量

937

审稿时长

3.8 months

期刊介绍： IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.