GT3: An Open-Source 3-nm GAAFET PDK and Platform for End-to-End Evaluation of Emerging Technologies

Abstract

In this article, we present a comprehensive end-to-end evaluation platform for various front-end-of-line (FEOL) and back-end-of-line (BEOL) technology options at the 3-nm technology node. Based on TCAD modeling of FE and BE, we have developed a 3-nm GAAFET-based process design kit (PDK). We have developed a 6-track standard cell library including 65 cells with a library height of 144 nm. Based on TCAD modeling of interconnects, we have evaluated the resistance of the entire BEOL stack using ruthenium for lower metal levels (M0–M3) and copper for higher metal levels (M4–M13). Based on place and route (PnR) studies using our PDK, we have analyzed the impact of high aspect ratio (AR) Ru interconnects at M2 and M3 in terms of performance using benchmark designs. Our results show that using Ru interconnects improves the circuit performance by up to 10.4% compared with Cu interconnects and that increasing the AR generally results in performance degradation due to the increase in capacitance and via resistances. We have observed a 5.9% and 4% degradation in performance for AES and LDPC, respectively, when moving from AR2 to AR6 local interconnects. However, adding an airgap can improve the higher AR Ru interconnect cases and AR4 with airgap case shows the most performance improvement with an overall 19.7% improvement compared with Cu. This case study also serves as an example that shows the importance of an end-to-end evaluation platform.