The Investigation of the Hysteresis and Reliability Mechanism of Amorphous Oxide Semiconductor Thin-Film Transistors Applied in Dynamic Random Access Memory

Abstract

In recent years, there has been significant interest in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). Multiple investigations have documented the advancement of AOS TFTs, which are utilized in 2T0C dynamic random access memory (DRAM). This work investigates the hysteresis and reliability performance of InGaZnO (IGZO) TFTs and InSnO (ITO) TFTs under different annealing conditions. ITO TFTs have superior electrical performance, with an extremely little hysteresis of practically zero volts and threshold voltage shifts of less than 0.07 V with negative and positive bias stress (PBS) lasting 1000 s. The analysis of hysteresis relies on considering the traps existing at the interface between the gate dielectric and the channel, the interface between the passivation layer and the channel, and electric dipoles. Meanwhile, the good reliability of ITO TFTs is attributed to the simple composition of the ITO channel and the change in valence state of Sn during annealing. The text discusses the illumination of the influence caused by the shifting of threshold voltage in 2T0C DRAM read transistors. ITO read transistors exhibit a retention duration that is more than seven times longer. This finding indicates that the ITO channel is a potential avenue for research within the realm of 2T0C DRAM.