{"title":"High-Performance Enhancement-Mode GaN p-FET Fabricated With an Etch-Stop Process","authors":"Hengyuan Qi;Teng Li;Jingjing Yu;Jiawei Cui;Junjie Yang;Sihang Liu;Yunhong Lao;Han Yang;Xuelin Yang;Maojun Wang;Bo Shen;Yamin Zhang;Shiwei Feng;Meng Zhang;Jin Wei","doi":"10.1109/TED.2025.3540053","DOIUrl":null,"url":null,"abstract":"The gate recess process for the enhancement-mode (E-mode) gallium nitride (GaN) p-FET is expected to create a high density of crystalline defects; thus, a large <inline-formula> <tex-math>$\\vert {V}_{\\text {th}} \\vert $ </tex-math></inline-formula> is often accompanied with a poor I<sc>on</small>. To address this challenge, in this work, an etch-stop process is developed with a 1.5-nm AlN layer inserted in the p-GaN layer, so the dry-etch-based gate recess is terminated at the AlN layer. The AlN at the recess region is then removed using a wet etch, so the surface of the gate channel is shielded from the plasma bombardment during the dry etch. The fabricated etch-stop GaN p-FET demonstrates an E-mode operation with a large <inline-formula> <tex-math>${V} _{\\text {th}} = -4.9$ </tex-math></inline-formula> V, a high I<sc>on</small> of 6.79 mA/mm, a small <inline-formula> <tex-math>${V} _{\\text {th}}$ </tex-math></inline-formula> hysteresis of 0.2 V, and a high I<sc>on</small>/I<sc>off</small> ratio of 106. Furthermore, an E-mode n-channel FET was fabricated on the same epitaxial wafer to demonstrate the potential of the proposed etch-stop p-FET technology for GaN complementary logic (CL). Therefore, the technology demonstrated in this work is proved an effective approach to address the <inline-formula> <tex-math>${V} _{\\text {th}}$ </tex-math></inline-formula>–I<sc>on</small> tradeoff in the GaN p-FET for CL applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1663-1668"},"PeriodicalIF":2.9000,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10891619/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The gate recess process for the enhancement-mode (E-mode) gallium nitride (GaN) p-FET is expected to create a high density of crystalline defects; thus, a large $\vert {V}_{\text {th}} \vert $ is often accompanied with a poor Ion. To address this challenge, in this work, an etch-stop process is developed with a 1.5-nm AlN layer inserted in the p-GaN layer, so the dry-etch-based gate recess is terminated at the AlN layer. The AlN at the recess region is then removed using a wet etch, so the surface of the gate channel is shielded from the plasma bombardment during the dry etch. The fabricated etch-stop GaN p-FET demonstrates an E-mode operation with a large ${V} _{\text {th}} = -4.9$ V, a high Ion of 6.79 mA/mm, a small ${V} _{\text {th}}$ hysteresis of 0.2 V, and a high Ion/Ioff ratio of 106. Furthermore, an E-mode n-channel FET was fabricated on the same epitaxial wafer to demonstrate the potential of the proposed etch-stop p-FET technology for GaN complementary logic (CL). Therefore, the technology demonstrated in this work is proved an effective approach to address the ${V} _{\text {th}}$ –Ion tradeoff in the GaN p-FET for CL applications.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.