Radiation Degradation and Mitigation of an Ultrathin SOI SPAD Using a Perimeter Gate

IF 2.9 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Electron Devices Pub Date : 2025-02-27 DOI:10.1109/TED.2025.3543789

Tom Klauner;Nicolas Roisin;Ottilie Bonfanti;Iman Sabri Alirezaei;Nicolas André;Denis Flandre

{"title":"Radiation Degradation and Mitigation of an Ultrathin SOI SPAD Using a Perimeter Gate","authors":"Tom Klauner;Nicolas Roisin;Ottilie Bonfanti;Iman Sabri Alirezaei;Nicolas André;Denis Flandre","doi":"10.1109/TED.2025.3543789","DOIUrl":null,"url":null,"abstract":"This work investigates the robustness of an ultrathin backside-illuminated (BSI) silicon-on-insulator (SOI) single-photon avalanche diode (SPAD) against gamma-ray irradiation for space applications. Experimental results demonstrate a breakdown voltage shift in the studied SPAD from 10.17 to 9.95 V after a total ionizing dose (TID) of 132 krad(Si). An increase in dark count rate (DCR) from 1490 to 2700 cps/<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m2 at 1 V excess bias is shown at this dose. TCAD simulations explain the role of the oxide-trapped charges, induced by irradiation in the insulating layer surrounding the active region, on the SPAD performance. These trapped charges shift the peak electric field, leading to premature breakdown while the extension of the active area affected by impact ionization increases the DCR. Further simulations show that implementing a perimeter-gated structure and reducing oxide thickness can effectively mitigate these effects by leveraging capacitive effects, preventing a breakdown voltage shift. The perimeter gate (PG) lowers the simulated DCR after irradiation from 2700 to 1365 cps/<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m2, thereby enhancing the radiation resilience of ultrathin SOI SPADs beyond a TID of 132 krad(Si).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1844-1850"},"PeriodicalIF":2.9000,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10906672/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

This work investigates the robustness of an ultrathin backside-illuminated (BSI) silicon-on-insulator (SOI) single-photon avalanche diode (SPAD) against gamma-ray irradiation for space applications. Experimental results demonstrate a breakdown voltage shift in the studied SPAD from 10.17 to 9.95 V after a total ionizing dose (TID) of 132 krad(Si). An increase in dark count rate (DCR) from 1490 to 2700 cps/

$\mu $

m2 at 1 V excess bias is shown at this dose. TCAD simulations explain the role of the oxide-trapped charges, induced by irradiation in the insulating layer surrounding the active region, on the SPAD performance. These trapped charges shift the peak electric field, leading to premature breakdown while the extension of the active area affected by impact ionization increases the DCR. Further simulations show that implementing a perimeter-gated structure and reducing oxide thickness can effectively mitigate these effects by leveraging capacitive effects, preventing a breakdown voltage shift. The perimeter gate (PG) lowers the simulated DCR after irradiation from 2700 to 1365 cps/

$\mu $

m2, thereby enhancing the radiation resilience of ultrathin SOI SPADs beyond a TID of 132 krad(Si).

查看原文本刊更多论文

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Transactions on Electron Devices 工程技术-工程：电子与电气

CiteScore

5.80

自引率

16.10%

发文量

937

审稿时长

3.8 months

期刊介绍： IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.