{"title":"Design of High-Performance Dual-Channel-Layered InGaZnO Thin-Film Transistors With Different Indium Contents","authors":"Muhpul Alip;Ablat Abliz;Da Wan","doi":"10.1109/TED.2025.3538524","DOIUrl":null,"url":null,"abstract":"In this study, dual-channel-layered amorphous indium gallium zinc oxide (a-IGZO) based thin-film transistors (TFTs) with different In contents were fabricated using the RF magnetron sputtering technique to improve the performance and stability of single-layer a-IGZO TFTs. The optimum electrical performance of the dual-channel layered a-IGZO (2:1:1)/a-IGZO (1:1:1) TFT was obtained at a low <inline-formula> <tex-math>${V}_{\\text {TH}}$ </tex-math></inline-formula> of 0.5 V, <inline-formula> <tex-math>${I}_{\\text {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{\\text {off}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$1\\times 10^{{8}}$ </tex-math></inline-formula>, low subthreshold swing (SS) of 0.35 V/decade, high <inline-formula> <tex-math>$\\mu _{\\text {FE}}$ </tex-math></inline-formula> of 40.5 cm2/Vs, and best stability with small <inline-formula> <tex-math>${V}_{\\text {TH}}$ </tex-math></inline-formula> shifts (1.4 and −1.2 V) under positive gate bias stress (PBS) and negative gate bias stress (NBS) test. This performance improvement, attributed to electron transfer from the a-IGZO (2:1:1) layer to the a-IGZO (1:1:1) layer, resulted in the accumulation of free carriers near at a-IGZO (2:1:1) and a-IGZO (1:1:1) interface. Thus, the charges were mainly concentrated within the barrier at the interface, improving performance (controlling <inline-formula> <tex-math>${V}_{\\text {TH}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${N}_{e}$ </tex-math></inline-formula>), while maintaining high <inline-formula> <tex-math>$\\mu _{\\text {FE}}$ </tex-math></inline-formula> in a-IGZO (2:1:1)/a-IGZO (1:1:1) TFTs. In addition, the oxygen interstitial defects (Oi) of a-IGZO TFTs were calculated, and the inherent mechanism of stability improvement was examined. The degradation caused by Oi increased with increasing In content in a-IGZO TFTs. Further analysis showed that dual-channel layered a-IGZO (2:1:1)/a-IGZO (1:1:1) TFTs significantly reduced Oi and suppressed electron capture at the interface, resulting in enhanced device stability. Overall, the findings of this study are valuable for the advancement of dual-channel-layered a-IGZO TFTs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1802-1808"},"PeriodicalIF":2.9000,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10880502/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this study, dual-channel-layered amorphous indium gallium zinc oxide (a-IGZO) based thin-film transistors (TFTs) with different In contents were fabricated using the RF magnetron sputtering technique to improve the performance and stability of single-layer a-IGZO TFTs. The optimum electrical performance of the dual-channel layered a-IGZO (2:1:1)/a-IGZO (1:1:1) TFT was obtained at a low ${V}_{\text {TH}}$ of 0.5 V, ${I}_{\text {on}}$ /${I}_{\text {off}}$ of $1\times 10^{{8}}$ , low subthreshold swing (SS) of 0.35 V/decade, high $\mu _{\text {FE}}$ of 40.5 cm2/Vs, and best stability with small ${V}_{\text {TH}}$ shifts (1.4 and −1.2 V) under positive gate bias stress (PBS) and negative gate bias stress (NBS) test. This performance improvement, attributed to electron transfer from the a-IGZO (2:1:1) layer to the a-IGZO (1:1:1) layer, resulted in the accumulation of free carriers near at a-IGZO (2:1:1) and a-IGZO (1:1:1) interface. Thus, the charges were mainly concentrated within the barrier at the interface, improving performance (controlling ${V}_{\text {TH}}$ and ${N}_{e}$ ), while maintaining high $\mu _{\text {FE}}$ in a-IGZO (2:1:1)/a-IGZO (1:1:1) TFTs. In addition, the oxygen interstitial defects (Oi) of a-IGZO TFTs were calculated, and the inherent mechanism of stability improvement was examined. The degradation caused by Oi increased with increasing In content in a-IGZO TFTs. Further analysis showed that dual-channel layered a-IGZO (2:1:1)/a-IGZO (1:1:1) TFTs significantly reduced Oi and suppressed electron capture at the interface, resulting in enhanced device stability. Overall, the findings of this study are valuable for the advancement of dual-channel-layered a-IGZO TFTs.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.