Evaluation of the impact of body bias on the threshold voltage drift of planar SiO2 transistors

IF 1.6 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability Pub Date : 2025-03-30 DOI:10.1016/j.microrel.2025.115693

Michael Waltl , Konstantinos Tselios , Theresia Knobloch , Dominic Waldhoer , Hubert Enichlmair , Eleftherios G. Ioannidis , Rainer Minixhofer , Tibor Grasser

{"title":"Evaluation of the impact of body bias on the threshold voltage drift of planar SiO2 transistors","authors":"Michael Waltl , Konstantinos Tselios , Theresia Knobloch , Dominic Waldhoer , Hubert Enichlmair , Eleftherios G. Ioannidis , Rainer Minixhofer , Tibor Grasser","doi":"10.1016/j.microrel.2025.115693","DOIUrl":null,"url":null,"abstract":"<div><div>The performance of semiconductor transistors is significantly influenced by charge trapping at oxide and interface defects. The impact of charge-trapping events of defects on the characteristics of the transistor is strongly dependent on factors such as the geometry and the operating point at which the transistor is used. Understanding the complex relationships between the influence of defects and the robustness of devices is essential to optimize circuit performance and becomes particularly important in analog designs. In this work, we investigate the influence of gate oxide defects on the reliability of nanoscale MOS transistors under varying body bias conditions. Using measure-stress-measure techniques, we observe notable effects on both time-zero and time-dependent variability with the application of body bias. Furthermore, the amplitudes of the step heights are investigated as they provide an important measure in scaled technologies to estimate the impact of traps on the device behavior. The results indicate that a body bias can be strategically employed to enhance device reliability by fine-tuning the body bias conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115693"},"PeriodicalIF":1.6000,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271425001064","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

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Abstract

The performance of semiconductor transistors is significantly influenced by charge trapping at oxide and interface defects. The impact of charge-trapping events of defects on the characteristics of the transistor is strongly dependent on factors such as the geometry and the operating point at which the transistor is used. Understanding the complex relationships between the influence of defects and the robustness of devices is essential to optimize circuit performance and becomes particularly important in analog designs. In this work, we investigate the influence of gate oxide defects on the reliability of nanoscale MOS transistors under varying body bias conditions. Using measure-stress-measure techniques, we observe notable effects on both time-zero and time-dependent variability with the application of body bias. Furthermore, the amplitudes of the step heights are investigated as they provide an important measure in scaled technologies to estimate the impact of traps on the device behavior. The results indicate that a body bias can be strategically employed to enhance device reliability by fine-tuning the body bias conditions.

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评估体偏压对平面二氧化硅晶体管阈值电压漂移的影响

半导体晶体管的性能受氧化物和界面缺陷的电荷捕获影响很大。缺陷的电荷捕获事件对晶体管特性的影响与晶体管的几何形状和工作点等因素密切相关。了解缺陷影响与器件稳健性之间的复杂关系对于优化电路性能至关重要，在模拟设计中尤为重要。在这项工作中，我们研究了栅极氧化物缺陷在不同体偏压条件下对纳米级 MOS 晶体管可靠性的影响。利用测量-应力-测量技术，我们观察到施加体偏压对时间零点和随时间变化的显著影响。此外，我们还对阶跃高度的振幅进行了研究，因为在按比例放大技术中，阶跃高度是估算陷波对器件行为影响的重要指标。结果表明，可以有策略地使用体偏压，通过微调体偏压条件来提高器件的可靠性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Reliability 工程技术-工程：电子与电气

CiteScore

3.30

自引率

12.50%

发文量

342

审稿时长

68 days

期刊介绍： Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.