Demonstration of High Transconductance Gate-All-Around Transistors Using Negative Capacitance ‘Super High-K’ Gate Stack

IF 4.1 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Electron Device Letters Pub Date : 2025-02-13 DOI:10.1109/LED.2025.3541547

Jong Ho Park;Nirmaan Shanker;Suraj Cheema;Shang-Lin Hsu;Aditya Varma;Chia-Chun Lee;Chirag Garg;Urmita Siker;Li-Chen Wang;Chenming Hu;Sayeef Salahuddin

引用次数: 0

Abstract

We demonstrate a gate all around (GAA) negative capacitance FET (NCFET). The device provides an equivalent oxide thickness (EOT) of 6.5Å with unscavenged SiO2 interlayer (IL), and a high transconductance of 2.15 mS/

$\mu $

m for L

${_{\text {eff}}} =45$

nm, matching and exceeding what has been reported for MOSFETs with much shorter gate lengths and similar gate stack thickness. Our results demonstrate feasibility of negative capacitance gate stack in a GAA geometry for enhanced gate control, scaling, and performance.

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来源期刊

IEEE Electron Device Letters 工程技术-工程：电子与电气

CiteScore

8.20

自引率

10.20%

发文量

551

审稿时长

1.4 months

期刊介绍： IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.