Scalable Vertical In–Ga–As Nanowire MOSFET With 67 mV/dec at 126μm Gate Width

IF 4.1 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Anette Löfstrand;Marcus E. Sandberg;Johannes Svensson;Lars Fhager
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引用次数: 0

Abstract

Heterogeneous integration of III-V narrow bandgap transistors on silicon technology is desirable for high frequency circuit implementations. Such high-speed transistors must, however, scale to large gate widths to be suitable for general circuit design. Averaging among many variable channels is a key challenge for nanowire devices. A simplified, but high-speed compatible, nanowire device process was developed here. It utilizes metal plugs to reduce complexity in the gate patterning step. It also implements a spin coated BCB low-k dielectric as top interlayer. A vertical In-Ga–As MOSFET with 1600 nanowire channels and 110 nm gate length achieved a minimum subthreshold swing of $\mathrm {67~\mathrm{mV/dec} }$ at $\mathrm {126~\mu \text {m} }$ gate width. The maximum transconductance was $\mathrm {0.88~\text {m}\text {S} /\mu \text {m}}$ at 0.5 V drain-source voltage, with $\mathrm {0.22~\text {m}\text {A} /\mu \text {m}}$ normalized drain current. These long-channel results are on par with state-of-the art, but achieved for a device scaled to unprecedented device width. In tandem with the BCB interlayer, these results promise a back-end-of-line compatible high-speed vertical nanowire technology for integration on silicon.
可扩展垂直In-Ga-As纳米线MOSFET, 67 mV/dec,栅极宽度为126μm
基于硅技术的III-V窄带隙晶体管异质集成是高频电路实现的理想选择。然而,这种高速晶体管必须扩展到较大的栅极宽度,才能适用于一般电路设计。在许多可变通道之间进行平均是纳米线器件的关键挑战。这里开发了一种简化但高速兼容的纳米线器件工艺。它利用金属插头,以减少复杂性,在浇口图案步骤。它还实现了一个自旋涂层的BCB低k介电体作为顶层中间层。具有1600纳米线通道和110 nm栅极长度的垂直In-Ga-As MOSFET在栅极宽度为$\mathrm {126~\mu \text {m}}$时实现了$\mathrm {67~\mathrm{mV/dec}}$的最小亚阈值摆幅。在0.5 V漏源电压下,$\mathrm {0.88~\text {m}\text {S} /\mu \text {m}}$的最大跨导值为$\mathrm {0.22~\text {m}\text {A} /\mu \text {m}}$归一化漏极电流。这些长通道结果与最先进的技术相当,但实现的设备缩放到前所未有的设备宽度。与BCB中间层相结合,这些结果有望实现后端兼容的高速垂直纳米线技术,用于硅上的集成。
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来源期刊
IEEE Electron Device Letters
IEEE Electron Device Letters 工程技术-工程:电子与电气
CiteScore
8.20
自引率
10.20%
发文量
551
审稿时长
1.4 months
期刊介绍: IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.
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