Understanding of GIDL-State Degradation (GSD): The Reliability Challenge in pFET Standby Mode for Sub-20-nm DRAM Technology

IF 4.1 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Electron Device Letters Pub Date : 2025-02-17 DOI:10.1109/LED.2025.3539678

Da Wang;Yong Liu;Longda Zhou;Yongkang Xue;Pengpeng Ren;Runsheng Wang;Zhigang Ji;Ru Huang

引用次数: 0

Abstract

With the recent industrial adoption of a new low-power standby mode in the sub-word line drivers (SWD), we report a reliability challenge that occurs on p-type pitch transistor in sub-20-nm DRAM technology introduced by the GIDL-state degradation (GSD). It is observed that GSD can surpass the off-state degradation (OSD) stress mode. By separating different types of traps, we clarified the physical mechanism of GSD. Based on the understanding, a defect-based compact model is developed and validated, providing DRAM designers with a tool to find a balance between power consumption and long-term reliability.

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对gidl状态退化（GSD）的理解：亚20nm DRAM技术pet待机模式的可靠性挑战

随着最近在子字线驱动器（SWD）中采用新的低功耗待机模式，我们报告了由gidl状态退化（GSD）引入的sub- 20nm DRAM技术中p型间距晶体管出现的可靠性挑战。观察到GSD可以超越非状态退化（OSD）应力模式。通过对不同类型陷阱的分离，阐明了GSD的物理机制。在此基础上，开发并验证了基于缺陷的紧凑模型，为DRAM设计人员提供了在功耗和长期可靠性之间找到平衡的工具。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Electron Device Letters 工程技术-工程：电子与电气

CiteScore

8.20

自引率

10.20%

发文量

551

审稿时长

1.4 months

期刊介绍： IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.