Weizhong Chen;Xiangwei Zeng;Ao Wu;Cheng Li;Zhengsheng Han
{"title":"A Snapback-Free and Fast-Switching SOI LIGBT With Integrated Double Self-Biased MOSFET","authors":"Weizhong Chen;Xiangwei Zeng;Ao Wu;Cheng Li;Zhengsheng Han","doi":"10.1109/LED.2025.3539708","DOIUrl":null,"url":null,"abstract":"A novel SOI-LIGBT integrating a Double Self-driving MOSFET (DSM) is proposed. The DSM consists of a Self-Biased P-MOS (SBP) with a shorted main gate and a Self-Biased N-MOS (SBN) with a shorted auxiliary gate. These components are designed to function without additional gate signals, and they are driven automatically by the operating state of the LIGBT. During forward conduction, the SBP (<inline-formula> <tex-math>${V}_{\\text {GS,{P}}} \\gt {V}_{\\text {thp}}$ </tex-math></inline-formula>) is turned off, whereas the SBN gradually turns on as the <inline-formula> <tex-math>${V}_{\\text {CE}}$ </tex-math></inline-formula> increases. The P-buried substrate of SBN creates a potential barrier for electron carriers, effectively eliminating the snapback effect. During reverse conduction, the SBP (<inline-formula> <tex-math>${V}_{\\text {GS,{P}}} \\lt {V}_{\\text {thp}}$ </tex-math></inline-formula>) is turned on, and the SBN is turned off, functioning as a P-MOS in series with a PN-junction diode. During turn-off, the SBP (<inline-formula> <tex-math>${V}_{\\text {GS,{P}}} \\lt {V}_{\\text {thp}}$ </tex-math></inline-formula>) and the SBN (<inline-formula> <tex-math>${V}_{\\text {GS,{N}}} \\gt {V}_{\\text {thn}}$ </tex-math></inline-formula>) are reactivated to extract excess carriers. Consequently, the DSM-LIGBT achieves a superior tradeoff between <inline-formula> <tex-math>${V}_{\\text {ON}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${E}_{\\text {OFF}}$ </tex-math></inline-formula>. At <inline-formula> <tex-math>${V}_{\\text {ON}} =1.22$ </tex-math></inline-formula> V, the <inline-formula> <tex-math>${E}_{\\text {OFF}}$ </tex-math></inline-formula> is reduced by 30%, 30.32%, and 68.23% compared with SBM-LIGBT, TBSA-LIGBT, and SSA-LIGBT, respectively.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"537-540"},"PeriodicalIF":4.1000,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10877907/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A novel SOI-LIGBT integrating a Double Self-driving MOSFET (DSM) is proposed. The DSM consists of a Self-Biased P-MOS (SBP) with a shorted main gate and a Self-Biased N-MOS (SBN) with a shorted auxiliary gate. These components are designed to function without additional gate signals, and they are driven automatically by the operating state of the LIGBT. During forward conduction, the SBP (${V}_{\text {GS,{P}}} \gt {V}_{\text {thp}}$ ) is turned off, whereas the SBN gradually turns on as the ${V}_{\text {CE}}$ increases. The P-buried substrate of SBN creates a potential barrier for electron carriers, effectively eliminating the snapback effect. During reverse conduction, the SBP (${V}_{\text {GS,{P}}} \lt {V}_{\text {thp}}$ ) is turned on, and the SBN is turned off, functioning as a P-MOS in series with a PN-junction diode. During turn-off, the SBP (${V}_{\text {GS,{P}}} \lt {V}_{\text {thp}}$ ) and the SBN (${V}_{\text {GS,{N}}} \gt {V}_{\text {thn}}$ ) are reactivated to extract excess carriers. Consequently, the DSM-LIGBT achieves a superior tradeoff between ${V}_{\text {ON}}$ and ${E}_{\text {OFF}}$ . At ${V}_{\text {ON}} =1.22$ V, the ${E}_{\text {OFF}}$ is reduced by 30%, 30.32%, and 68.23% compared with SBM-LIGBT, TBSA-LIGBT, and SSA-LIGBT, respectively.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.