Analytical modeling of nanoscale double-gate junctionless transistors comprising the impact of the source and drain underlap regions

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-03-25 DOI:10.1016/j.sse.2025.109105

Miltiadis K. Nakos , Andreas Tsormpatzoglou , Dimitrios H. Tassis , Theodoros A. Oproglidis , Constantinos T. Angelis , Charalabos A. Dimitriadis

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Abstract

In this study, we investigate the impact of the source and drain (S/D) underlap regions on the electrical characteristics of short-channel double-gate junctionless transistors (DG JLTs). Analytical expression for the potential distribution in the gate overlap and S/D underlap regions is introduced, which relies on a single fitting parameter and the gate fringe capacitance in the underlap regions. The derived potential distribution shows good agreement with simulation results across different underlap lengths and gate/drain bias voltages. Consequently, new expressions for the threshold voltage and the subthreshold swing coefficient of DG JLTs are developed comprising the effect of the S/D underlap regions, which are used for upgrading our previous continuous and symmetric analytical drain current compact model. The findings highlight the significant influence of the S/D underlap regions on the electrical characteristics of DG JLTs, suggesting a need for their careful consideration in drain current compact modeling.

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纳米级双栅无结晶体管的解析建模，包括源极和漏极下搭区影响

在这项研究中，我们研究了源极和漏极（S/D） underlap区域对短通道双栅无结晶体管（DG jlt）电特性的影响。给出了栅极重叠和S/D重叠区域电位分布的解析表达式，该表达式依赖于单一拟合参数和重叠区域的栅极条纹电容。推导出的电势分布与仿真结果在不同的下搭接长度和栅极/漏极偏置电压下吻合较好。因此，我们开发了DG jlt的阈值电压和亚阈值摆动系数的新表达式，其中包括S/D underlap区域的影响，用于改进我们之前的连续和对称解析漏极电流紧凑模型。研究结果强调了S/D underlap区域对DG jlt电特性的重要影响，表明在漏极电流紧凑建模中需要仔细考虑它们。

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.