Reducing MoS2 FET contact resistance by stepped annealing to optimize device performance†

Abstract

Transition metal dichalcogenides (TMDCs), especially MoS₂, are essential materials that are seen as the future of the electronics industry going forward. It's acknowledged that annealing is usually required when the fabrication of MoS₂-based devices inevitably introduces contaminants, resulting in poor contact. However, conventional annealing hardly improves the interfacial contact between metal electrodes and MoS₂. In this work, MoS₂ back-gate field effect transistors are prepared on the basis of prepared high-quality single-crystal MoS₂ by CVD. Innovative stepped annealing was applied to device optimization to improve interfacial contact and electrical performance. The optimum device annealing temperature in an Ar atmosphere is 300 °C, at which the interface contact resistance is reduced from 209.3 kΩ μm to 4.7 kΩ μm compared to the pristine state. Decrease in the Schottky barrier height plays a key role in improving interfacial contact and electrical properties. After stepped annealing treatment, the device on/off ratio is improved by two orders of magnitude, the subthreshold swing is reduced by approximately 80%, and the field effect mobility is improved by approximately 10 times. This work is crucial for device annealing and high performance MoS₂-based transistor devices.