Low Capacitance and Fast Response SCR for High-Speed I/O ESD Protections

IF 4.1 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Electron Device Letters Pub Date : 2025-02-18 DOI:10.1109/LED.2025.3542844

Ruibo Chen;Feibo Du;Lu Li;Zhiwei Liu;Zhangming Zhu

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引用次数: 0

Abstract

A floating-base N-type transistor triggered silicon-controlled rectifier (FBNTSCR) device is developed for high-speed I/O electrostatic discharge (ESD) protection. The device, constructed by embedding a floating-base N-type transistor as the trigger element replacing the P-well tie in a standard SCR, enables the embedded bipolar to be avalanched at the collector-emitter breakdown voltage, providing a lower trigger voltage than the conventional LVTSCR. Furthermore, a lower parasitic capacitance is achieved by mitigating the capacitance associated with the N-well/P-well junction. The proposed design also has a shorter inherent SCR path, resulting in lower on-resistance, higher failure current (

$l_{{t}{2}}$

) and lower overshoot voltage as well as faster turn on speed, all of which benefit the CDM ESD protection performance. Measurement results show the FBNTSCR has ~40.8% reduced trigger voltage, ~68.9% reduced parasitic capacitance and ~16.7% enhanced

$l_{{t}{2}}$

compared to the conventional LVTSCR.

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来源期刊

IEEE Electron Device Letters 工程技术-工程：电子与电气

CiteScore

8.20

自引率

10.20%

发文量

551

审稿时长

1.4 months

期刊介绍： IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.