A PMOS-embedded low-voltage triggered silicon controlled rectifier ESD protection device for 3.3V I/O application

IF 1.6 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability Pub Date : 2025-03-24 DOI:10.1016/j.microrel.2025.115706

Jun Deng, Hongjiao Yang, Yang Wang, Fengfeng Zhou, Haotian Chen, Beibei Nie, Wei Liu

{"title":"A PMOS-embedded low-voltage triggered silicon controlled rectifier ESD protection device for 3.3V I/O application","authors":"Jun Deng, Hongjiao Yang, Yang Wang, Fengfeng Zhou, Haotian Chen, Beibei Nie, Wei Liu","doi":"10.1016/j.microrel.2025.115706","DOIUrl":null,"url":null,"abstract":"<div><div>In this paper, a novel low-trigger-voltage and high-robustness Electrostatic Discharge (ESD) protection device, called PMOS-embedded Low-Voltage Triggered Silicon Controlled Rectifier (PLVTSCR), is proposed for 3.3V I/O protection application in 0.18 μm CMOS process. The first improved PLVTSCR is called PLVTSCR-A. It is achieved by introducing a PMOS into the traditional SCR to provide a trigger current for SCR, thereby reducing the traditional SCR's trigger voltage (<em>V</em><sub>t1</sub>) and further increasing the failure current (<em>I</em><sub>t2</sub>) by utilizing the PMOS to introduce an additional parasitic SCR path. The second improved PLVTSCR is called PLVTSCR-B. The difference between PLVTSCR-B and PLVTSCR-A is that PLVTSCR-B does not have the DNW layer, making the base region of the parasitic NPN open circuit, further reducing PLVTSCR-A's trigger voltage. The third device is called PLVTSCR-C. PLVTSCR-C is another layout structure of PLVTSCR-B, and it can increase the holding current (<em>I</em><sub>h</sub>) and holding voltage of the device without increasing the area. The proposed series of devices can significantly improve the ESD characteristics of traditional SCR. Measurement results show that the PLVTSCR-C's trigger voltage is reduced by 51.5 %, and the failure current is increased by 10.3 % compared to traditional SCR. Furthermore, the holding current of PLVTSCR-C is 328.5 mA, which is much higher than the current during normal operation of the circuit and can effectively prevent latch-up. Additionally, the new device is expected to protect 3.3V I/O in deep submicron technology and has been implemented in a 0.18 μm CMOS process.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115706"},"PeriodicalIF":1.6000,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271425001192","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

In this paper, a novel low-trigger-voltage and high-robustness Electrostatic Discharge (ESD) protection device, called PMOS-embedded Low-Voltage Triggered Silicon Controlled Rectifier (PLVTSCR), is proposed for 3.3V I/O protection application in 0.18 μm CMOS process. The first improved PLVTSCR is called PLVTSCR-A. It is achieved by introducing a PMOS into the traditional SCR to provide a trigger current for SCR, thereby reducing the traditional SCR's trigger voltage (V_t1) and further increasing the failure current (I_t2) by utilizing the PMOS to introduce an additional parasitic SCR path. The second improved PLVTSCR is called PLVTSCR-B. The difference between PLVTSCR-B and PLVTSCR-A is that PLVTSCR-B does not have the DNW layer, making the base region of the parasitic NPN open circuit, further reducing PLVTSCR-A's trigger voltage. The third device is called PLVTSCR-C. PLVTSCR-C is another layout structure of PLVTSCR-B, and it can increase the holding current (I_h) and holding voltage of the device without increasing the area. The proposed series of devices can significantly improve the ESD characteristics of traditional SCR. Measurement results show that the PLVTSCR-C's trigger voltage is reduced by 51.5 %, and the failure current is increased by 10.3 % compared to traditional SCR. Furthermore, the holding current of PLVTSCR-C is 328.5 mA, which is much higher than the current during normal operation of the circuit and can effectively prevent latch-up. Additionally, the new device is expected to protect 3.3V I/O in deep submicron technology and has been implemented in a 0.18 μm CMOS process.

查看原文本刊更多论文

求助全文

约1分钟内获得全文求助全文

来源期刊

Microelectronics Reliability 工程技术-工程：电子与电气

CiteScore

3.30

自引率

12.50%

发文量

342

审稿时长

68 days

期刊介绍： Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.